1. Field of the Invention
The present invention relates to a correlating filter for use in a receiver for the code division multiple access (CDMA) communication using the spectrum spread communication, and a CDMA receiver, and in particular, to a correlating filter and a CDMA receiver for improving the power consumption.
2. Description of the Related Art
In the CDMA communication system using the spectrum spread communication, the spectrum utilization is largely improved as compared with frequency division multiple access (FDMA) communication systems or time division multiple access (TDMA) communication systems. For this reason, various practical techniques have been recently proposed.
In a communication device, particularly a receiver, for despreading communication, a correlating filter is used at times for an despreading process relative to a received signal.
For example, FIG. 7 shows a schematic structure of a conventional receiver. In this receiver, a correlation process is applied to a received signal by a correlating filter 20 and then a decoding process is applied by a decoding circuit 21 to a correlated output signal where a correlation of a given condition is achieved, so that a decoded received signal is obtained.
As a processing method achieved by the correlating filter of this kind, there have been a method where a correlation process is performed in an intermediate frequency band using a correlating filter including a SAW device and a method where a correlating filter is used for processing a base band signal after orthogonal detection.
Hereinbelow, the correlating filter for processing the base band signal after the orthogonal detection will be explained.
FIG. 6 shows a schematic structure of a correlating filter of this kind. As shown in the figure, the correlating filter includes a delay circuit 22 and a weighted adder circuit 23.
The correlating filter is provided, for example, before the decoding circuit 21 as shown in FIG. 7 so as to achieve a correlation relative to a base band signal.
FIG. 6, the delay circuit 22 is provided for outputting delayed signals relative to an input signal. When the input signal is a digital signal, the delay circuit 22 is constituted by, for example, a shift register. On the other hand, when the input signal is an analog signal, the delay circuit 22 is constituted by, for example, delay lines and an analog shift register.
FIG. 9 shows a known structure of an analog shift register. In FIG. 9, a plurality of sample hold circuits 24 having the same structure are coupled in cascade connection to each other, and each sample hold circuit is arranged to produce a delayed output.
FIG. 10 shows a known structure of the sample hold circuit 24. As shown in FIG. 10, the sample hold circuit 24 includes switches 25a and 25b which are turned on and off synchronously with a clock signal (CK), buffer circuits 26a to 26c coupled in cascade connection to each other via the switches 25a and 25b, and capacitors 27a and 27b connected to input terminals of the buffer circuits 26b and 26c, respectively.
An operation of the thus arranged sample hold circuit will be briefly explained with reference to a timing chart shown in FIG. 11. The switches 25a and 25b are turned on at a leading edge (from low level to high level) of the clock signal and turned off at a trailing edge (from high level to low level) of the clock signal.
When a signal Sin inputted to the buffer circuit 26a repeats gradual increase and gradual decrease in signal level with a lapse of time as shown at (b) in FIG. 11, a signal variation appearing at an output point (point A in FIG. 10) of the buffer circuit 26b becomes as shown at (c) in FIG. 11 since the so-called integrated output is obtained.
Since the output signal of the buffer circuit 26b is stored at the capacitor 27b via the switch 25b and outputted via the buffer circuit 26c, an output signal Sout becomes a stepwise sampled signal as shown at (d) in FIG. 11.
FIG. 12 shows a known structure of the buffer circuit 26a to 26c, wherein a so-called voltage follower including an operational amplifier 28 is used.
FIG. 13 shows another known structure of the buffer circuit 26a to 26c. In FIG. 13, a signal Sin is inputted to an inverted input terminal of an operational amplifier 28 via an impedance element 29a, and a feedback impedance element 29b is connected between the inverted input terminal and an output terminal of the operational amplifier 28 so as to form a so-called inverting amplifier.
FIG. 14 shows a known structure of the weighted adder circuit 23 (see FIG. 6). In FIG. 14, the weighted adder circuit 23 includes a plurality of weighting circuits 30 provided corresponding to tap outputs TP1 to TPn from the delay circuit 22 (see FIG. 6) and performing multiplication between the tap outputs TP1 to TPn and weighting coefficients W1 to Wn, and an adder circuit 31 which synthesizes output signals from the respective weighting circuits 30 to produce a correlated output signal.
When using a digital signal, it is preferable to constitute the weighting circuit 30 by a digital multiplier. On the other hand, when using an analog signal, it is preferable to constitute the weighting circuit 30 mainly by an operational amplifier 28 as shown in FIG. 15.
In FIG. 15, the weighting circuit includes a plurality of impedance elements 32a provided corresponding to bits of a weighting coefficient in binary notation and a plurality of switches 33 provided corresponding to bits of a weighting coefficient in binary notation same as the impedance elements 32a. Between an input terminal of the weighting circuit and an inverted input terminal of an operational amplifier 28, each of the impedance elements 32a and the corresponding switch 33 are connected in series while these series circuits are connected in parallel to each other.
A non-inverted input terminal of the operational amplifier 28 is grounded, while a feedback impedance element 32b is connected between the inverted input terminal and an output terminal of the operational amplifier 28, so that an inverted amplification is achieved.
ON/OFF states of the switches 33 are controlled corresponding to binary digits of the weighting coefficient. Assuming that the switch 33 located at the uppermost portion in FIG. 15 corresponds to the most significant bit of the weighting coefficient in binary notation, values of the impedance elements 32a are so set as to increase in order from the uppermost toward the lower impedance elements 32a. In other words, a value of the impedance element 32a connected to the switch 33 corresponding to the most significant bit is set to be minimum.
Accordingly, through ON/OFF operations of the switches 33 corresponding to the weighting coefficient, a value of impedance at the inverted input terminal of the operational amplifier 28 is changed. When capacitors are used as the impedance elements 32a and the feedback impedance element 32b, a gain G of the whole circuit is given by: EQU G=Ci/Cf
wherein Ci (i=1 to n) represents a capacitance of each capacitor as the impedance element 32a, and Cf represents a capacitance of the capacitor as the feedback impedance element 32b.
Thus, an input signal TPin is weighted by the sum of the impedance elements 32a depending on the ON/OFF states of the switches 33 and, after amplification, outputted as a weighted output signal Eout.
The adder circuit 31 (see FIG. 14) is preferably formed by a so-called digital adder when a digital signal is used. On the other hand, when using an analog signal, the adder circuit 31 is preferably formed by an analog adder as shown in FIG. 16.
In FIG. 16, the analog adder is basically formed by an inverting amplifier including an operational amplifier 28. Specifically, a plurality of signals Sin 1 to Sin n are inputted to an inverted input terminal of the operational amplifier 28 via corresponding impedance elements 34 so that the inputted signals are added and an output signal Sout corresponding to an inverted value of the sum of the inputted signals are obtained.
The correlating filter 20 (see FIG. 7) having the foregoing structure is constantly inputted with the received signal and, when the received signal has a given correlation, the correlating filter 20 outputs a correlated output signal (see .alpha., .beta. in FIG. 8) with a large output level and a small output time width, similar to a so-called impulse signal. Theoretically, one largest correlated output signal is produced at a given position as corresponding to .alpha. or .beta. in FIG. 8. However, in practice, since dispersion of the correlation peak is caused, signals with smaller levels than the correlated output signal are produced in the neighborhood thereof (see FIG. 8).
The correlated output signal thus obtained is decoded in the decoding circuit 21 (see FIG. 7) so that a desired received signal is obtained.
On the other hand, the signal necessary for decoding in the decoding circuit 21 corresponds to just the portions identified by .alpha. and .beta. in FIG. 8 where the largest correlation peaks are achieved, so that the other portions are not necessary.
In general, the constant operation of the correlating filter is only required at a particular case, such as upon initial acquisition of synchronism or upon interference level measurement.
However, the conventional correlating filter and decoding circuit are constantly set in operation so that the wasteful power consumption has been caused.
Particularly, the correlating filter for processing the base band signal after the orthogonal detection requires a relatively large number of the circuit parts as described above, so that the larger power consumption is required as compared with the other circuits. This can not be ignored particularly in a portable radio device using a battery as a power supply. Actually, such a correlating filter can not be used in the portable radio device.
On the other hand, the foregoing conventional correlating filter using the SAW device requires a far greater mounting area on a printed board as compared with TV SAW filters or other semiconductor devices, so that reduction in size is very difficult. This raises a problem since such a correlating filter is not suitable for the portable radio device, particularly, using the CDMA communication system for which various practical techniques have been recently proposed.